SAN JOSE, CA--(MARKET WIRE)--Sep 25, 2008 --

 
What:  Low-Power Design Summit
When:  Oct. 1, 2008, 8 a.m. to 7 p.m.
Where: Cadence Design Systems, Inc. (CDNS - News), Pebble Beach Conference
       Room in Bldg. 5, 2655 Seely Ave., San Jose, CA 95134
Press Registration: Contact Niki Tran at nikitran@cadence.com
       or (408) 428-5159

Join designers of energy-efficient chips and systems as they learn about successful low-power design from their Power Forward Initiative (PFI) member peers. Hear keynote addresses from NVIDIA CTO Chris Malachowski and Silicon Valley Leadership Group President and CEO Carl Guardino. Check out low-power ecosystem offerings from EDA, IP, foundry, IDM, ASIC and design service companies. Catch the perspective of project managers who have completed low-power designs and from distinguished panelists as they discuss the future of power-efficient design. For more information see http://www.powerforward.org/

 
Agenda:
8 a.m.          Registration and breakfast
9 - 9:30        Keynote: Chris Malachowski, co-founder and Sr. VP of NVIDIA
9:30 - 11:30    Technical sessions by PFI members
11:30 - 12:30   Panel: "Deploying Power: What are the Challenges?"
12:30 - 1:30    Lunch
1:30 - 3:30     Technical sessions by PFI members
3:30 - 4:40     Keynote: Carl Guardino, president and CEO of SVLG
4:00 - 4:40     Panel: "Enabling Power Efficient Design: How Important is
                it to be Green?"
4:40 - 6 p.m.   Closing remarks, drinks and tabletop exhibits

About the PFI

Recognizing the urgent need for an automated, power-aware design infrastructure, industry leaders are collaborating through the Power Forward Initiative to drive the refinement and adoption of advanced Common Power Format-enabled low-power design methodologies. Members include Alchip, AMD, Applied Materials, ARC, ARM, Azuro, Cadence, Calypto, Denali, DNP, Faraday, Freescale, Fujitsu, Global Unichip, Globetech, Improv Systems, Mindtree, MIPS Technologies, NEC Electronics, NSW, NXP, Sequence, SMIC, Socle, Sonics, Tensilica, Toppan, TSMC, UMC, VeriSilicon, Virage Logic, Vivace, and Wipro.

     For more information, please contact:
     Dan Holden
     Power Forward Initiative
     408-960-5159
     holden@cadence.com