The following discussion and analysis should be read in conjunction with our consolidated financial statements and related notes thereto included in Item 8 and the Risk Factors included in Item 1A of this annual report.

Executive Overview

Company and Market Overview

We are a global semiconductor company, serving over 13,000 customers in communications, computer and storage, industrial, and consumer market segments. We design, manufacture, and market a variety of products:

† Programmable logic devices (PLDs), which consist of field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs), are standard semiconductor integrated circuits, or chips, that our customers program to perform desired logic functions in their electronic systems.

† HardCopy application-specific integrated circuit (ASIC) devices transition customer designs from high-density FPGAs to low-cost non-programmable devices for volume production.

† Pre-defined design building blocks known as intellectual property (IP) cores can be licensed by customers to easily implement standard functions in their PLD designs.

† Associated development tools are used to develop designs and program our PLDs.

In 2008, sales of PLDs generated over 90% of our revenue, with FPGA and CPLD sales comprising approximately 74% and 18% of total revenue, respectively. The remainder of our sales is comprised of our HardCopy devices and configuration devices used in conjunction with our FPGAs, as well as licensing of IP cores and proprietary development tools.

Challenging Business Environment

The global financial crisis is characterized by significant disruption in the banking system and financial markets, decreased consumer confidence, reduced corporate profits and capital spending, concerns about inflation and deflation, and slower overall economic activity. As a result, the semiconductor industry, including the PLD segment, has, in recent months, experienced a significant slowdown in customer orders and overall demand. As has been the case in prior "down cycles" within the semiconductor industry, it is difficult to predict the severity and duration of the business downturn, as well as the timing or rate of business recovery. We agree with many industry observers that the current recession will endure throughout most of 2009, followed by a slow rate of recovery over the next two to three years. Consequently, we project our total revenue in 2009 to be less than total revenue in 2008, and our annualized growth rate during the subsequent two or three years to be less than we have experienced in recent years (our compound average growth rate in the past 5 years has been 11%).

Strong and Resilient Financial Business Model

Since the PLD market was created in the 1980s, the financial business models of the leading PLD suppliers have generally been favorable when compared to most other semiconductor companies. High sales growth rates, fabless strategies, high barriers to entry, and proprietary architectures have helped drive strong financial results for PLD suppliers.

As the semiconductor industry and the PLD market have matured, revenue growth in the PLD segment, while still higher than many other semiconductor segments, has slowed. In recent years, we have increased our focus on enhancing our business model despite slower revenue growth. Through various programs to improve R&D and SG&A productivity, as well as a general movement to simplify our business processes, we have been able to achieve higher rates of net income as a percentage of total revenue and a higher return on equity. As illustrated in the following table, these results have been achieved while also growing PLD market share.

  Net sales                                         $ 1,367   $  827               11%

  Net income                                        $   360   $  152               19%

  Diluted income per share                          $  1.18   $ 0.39

  PLD market share                                      36%      32%

  FPGA market share                                     34%      29%

(1) Compound annual growth rate

We believe that our early focus on cost reduction and productivity enhancement before the business slowdown related to the current global financial crisis may provide us some benefits compared to other semiconductor companies. Our ability to maintain investment in the research and development of future products, which has been aided by our early and ongoing cost savings initiatives, is a vital factor for our future growth. In addition, our prior work in analyzing business processes has not only allowed us to effectively identify and execute areas for simplification and cost reduction, but the concept of "workflow efficiency" is an increasingly valued aspect of our business culture. This work and our evolving culture may be an asset as we navigate our company through the current recession.

Market Opportunity

We believe that our greatest opportunity for growth is displacing ASICs and ASSPs. Based on publicly available data and information derived from Gartner Dataquest, we estimate that the PLD market was approximately $3.8 billion in 2008, and that the digital logic market, consisting primarily of ASICs and ASSPs, was approximately $35.0 billion. Because PLDs can be quickly programmed by the customer to perform the specific function needed by the customer, PLDs provide greater advantages in flexibility, development cost, and time-to-market than ASIC and ASSP alternatives. Because PLDs generally have a higher cost structure than these alternatives, they are particularly favored in applications where there is a substantial time-to-market advantage and where unit volumes are low. Some customers develop and prototype their system with PLDs for their time-to-market benefits and then redesign to an ASIC to reduce costs as volume increases. Due to greater architectural innovation and faster adoption of advanced process technology, we believe that customers will increasingly favor PLDs over ASICs and ASSPs because:

† Advances in PLD technology and in semiconductor manufacturing technology are lowering the relative cost, performance, and power consumption differential between PLDs and fixed-chip alternatives

† We are increasingly successful in selling PLDs into applications and markets that have been traditionally served by ASICs and ASSPs

† We can compete successfully for customer volume production needs as well as their initial prototyping and development needs

The PLD market peaked at approximately $4.1 billion in 2000 and declined over the next two years to approximately $2.3 billion in 2002. From 2003 to 2008, the PLD market has grown with a compound average growth rate of approximately 8%. Due to the broad PLD customer base, the diverse PLD market segments, and the unpredictable nature of end customer demand, future PLD market growth rates are difficult to forecast and may be lower than in recent years. PLD market growth will be driven by the growth of PLD prototyping and production opportunities.

The two leading PLD vendors serve an extremely large and diverse customer base and the opportunity to expand the number of customers may be limited. As a result, a critical objective for PLD vendors is not simply to add more prototyping customers, but to penetrate customers and end markets in high-volume applications. PLD vendors' ability to achieve higher production volume is contingent upon several factors, including their ability to offer cost-effective

solutions versus ASICs and ASSPs, and end customer demand. Publicly available data suggests that the number of ASIC design starts is in decline which may drive an increase in the number of high volume PLD applications.

Competing for Design Wins

We compete with other PLD vendors to displace fixed-chip logic alternatives and for market share within the PLD market. Competition between PLD vendors is most intense in the "design-win" phase of the customer's design, when customers select products for use in the customer's electronic system. Because each PLD vendor's products are proprietary, the cost to switch PLDs after a system has been designed and prototyped is very high. Therefore, a design win can provide the PLD vendor with a profitable revenue stream through the life of the customer's program.

From the time a design win is secured, it can be two or more years before a customer starts volume production of its system. Typically, the customer selects the PLD vendor relatively early in a customer's design process, but it may take several years to complete system design, build prototypes, sampled the marketplace for customer acceptance, make modifications, and manufacture in volume. Thus, there is a delay between developing a competitive advantage to a shift in the PLD market, meaning that market share is a lagging indicator of relative competitive strength. Because it is extremely difficult to forecast the success and timing of customer programs, and because the end markets are so fragmented (we have over 13,000 PLD customers), it is difficult even for PLD vendors to gauge their own competitive strength in winning designs at a particular point in time.

Developing Competitive Products

A PLD vendor's ability to secure design wins and to maintain or increase market share is highly dependent on the cost and quality of its products, particularly the effectiveness and reliability of its proprietary development software. All PLD vendors provide proprietary development software at little or no cost to the customer. The software, working in tandem with device logic architecture and features, creates the functionality desired by the customer. As customers gain familiarity with a particular PLD vendor's software, they often want to use that same software again in another design, giving that PLD vendor a potential advantage as the next system is designed. We develop our software in parallel with our devices, and there are schedule and integration risks between the two processes. If we fail to create adequate software to support our new devices as they are introduced, we weaken our competitive position, which can have long-lasting effects if customers switch to competing solutions and become less familiar and less skilled with our software.

We focus the majority of our research and development resources on new-generation FPGAs because increasing our FPGA market share is important to our long-term growth and profitability. Due to the higher integration density and lower cost per function, the FPGA market has outgrown the CPLD market in recent times, and industry participants and observers believe this trend will continue. Since the initial introduction of our Stratix and Cyclone FPGA families in 2002, we have introduced several more FPGA families, including the Stratix II, Stratix II GX, Stratix III, Stratix IV, Stratix IV GX, Cyclone II, Cyclone III, and Arria GX families. As a result of these product introductions, we estimate, based on publicly available data and with information derived from Gartner Dataquest, that our market share has increased as follows:

                             Market Share   2008   2003
                             PLD             36%    32%

                             FPGA            34%    29%

                             CPLD            40%    39%

Complementing our Stratix FPGAs is our HardCopy family of ASICs. We first shipped HardCopy devices in 2001, offering customers low-cost, non-programmable production devices that use our highest density FPGAs as an integrated development vehicle. Converting the FPGA design is virtually seamless and requires very little additional customer engineering. HardCopy devices are targeted specifically at those applications and customers that have used PLDs for prototyping and development and traditional cell-based ASICs from other vendors for their volume production needs. In 2008, our HardCopy ASIC revenues were less than 5% of total revenue, and we believe the HardCopy family may increase as a percentage of revenues over the long term.

The availability of a HardCopy conversion path for high-density FPGA designs is a competitive advantage. Since 2001, we have introduced newer versions of the HardCopy family to support newer generations of FPGAs. Our

approach is unique in the industry and may underperform our expectations. As we develop new generations of FPGAs, we may create parallel HardCopy devices, which would entail ongoing engineering effort and expense.

We have improved our CPLD offering by introducing the MAX II family in 2004 and the MAX IIZ family in 2007. MAX II CPLDs offer pricing and features that we believe are competitively attractive, with cost, performance, power consumption, and density that are superior to our previous offerings.

An FPGA family typically reaches peak sales four to five years after product introduction. As a result, the Stratix II and Cyclone II families we introduced in 2004, which comprised approximately 28% of total sales in 2008, may be at or near peak sales. We expect the products we introduced from 2005 to 2008 have yet to reach peak sales, but will eventually experience sales declines. To improve or even sustain our growth rate, we must successfully introduce successor generations of devices. The degree to which other PLD vendors improve the competitiveness and execution of their products may impair our ability to improve our growth rate.

Within the next several quarters, we plan to ship newer FPGA families using more advanced production techniques that will further improve product performance and lower cost. Our foundry partner, Taiwan Semiconductor Manufacturing Company ("TSMC"), will manufacture these die using production processes that are new to the industry. Given the extreme complexity of semiconductor fabrication, TSMC may encounter difficulties that could delay our product launch or limit supply so that we would be unable to meet customer commitments. We may discover manufacturing errors after we begin shipping, which would harm customer relations and cause us to incur additional unforeseen costs. Simultaneous introduction of new PLD architectures and ramp of new technology processes are inherently risky. Diagnosing failures, identifying root causes, and implementing corrective actions in a production wafer fabrication facility are expensive and time-consuming. We may not successfully commercialize our new products, or our new products may not enable us to maintain or increase market share. Some of our competitive offerings may be offered later than the competition and it is possible that our competitive offerings will be less effective, thus weakening our market share.

It is also possible that our primary competitor may have secured design wins that, when they enter production, will reverse some of our current market share success. Our main competitor is larger in size with more sales resources, and we may not enjoy the same success that we saw with previous FPGA generations.

Customer Intimacy and Cost-Optimized Product Strategy

We rely on customer interaction to gain product development insights, and we make development decisions years before a product begins to ship. We have been able to gain market share on the strength of our product definition methodology and the successful rollout of new products. However, because our products are complex, we assume considerable risk with every new product introduction. If we misinterpret customer requirements or demand changes, our products may become uncompetitive. Our competitors are knowledgeable and skilled and, in some cases, larger than we are. Since it is difficult to gauge competitive success until the design-win phase is well underway, it may be too late to make changes to a generation of products if those products are uncompetitive. If a product generation is uncompetitive and we lose market share, regaining customers is very challenging.

Since 2002 and following the semiconductor industry correction, our strategy to displace ASICs and ASSPs has emphasized the development of cost-optimized products. These products have contributed to growth across all of our market segments and are increasingly being used by our customers in production volumes, not just as prototyping or low-volume solutions. Production volumes vary by industry, but customers buying our products in production volumes expect lower unit pricing. Consequently, our business today is subject to a wider gross margin range than the gross margin range associated with a less diverse, largely prototyping business. Depending on the mix of high- and low-volume business, our gross margins can vary more quarter to quarter than in the past. Since the majority of our business books and ships in the same quarter, forecasting our gross margins has also become more difficult. While we believe that growth will occur across all of our market segments, our gross margins could move up or down if our growth pattern favors low-volume or high-volume applications.

Critical Accounting Estimates

The preparation of our consolidated financial statements and related disclosures in conformity with accounting principles generally accepted in the United States ("U.S.") requires our management to make judgments and estimates that affect the amounts reported in our consolidated financial statements and accompanying notes. Our management believes that we consistently apply these judgments and estimates and the consolidated financial statements and accompanying notes fairly represent all periods presented. However, any differences between these judgments and estimates and actual results could have a material impact on our consolidated statements of income and financial condition. Critical accounting estimates, as defined by the Securities and Exchange Commission ("SEC"), are those that are most important to the portrayal of our financial condition and results of operations and require our management's most difficult and subjective judgments and estimates of matters that are inherently uncertain. Our critical accounting estimates include those regarding (1) revenue recognition;
(2) valuation of inventories; (3) income taxes; and (4) stock-based compensation.

Revenue Recognition

We sell our products to original equipment manufacturers, or OEMs, and to electronic components distributors who resell these products to OEMs, or their subcontract manufacturers. We sell more than 90% of our products to distributors for subsequent resale to OEMs or their subcontract manufacturers. In almost all cases, sales to distributors are made under agreements allowing for subsequent price adjustments and returns, and we defer recognition of revenue until the products are resold by the distributor. Our revenue reporting is highly dependent on receiving pertinent and accurate data from our distributors in a timely fashion. Distributors provide us with periodic data regarding the product, price, quantity, and end customer when products are resold as well as the quantities of our products they still have in stock. Because the data set is so large and because there may be errors in the reported data, we must use estimates and apply judgments to reconcile distributors' reported inventories to their activities. This reconciliation process requires us to estimate the amount of in-transit shipments (net of in-transit returns) to our distributors. In-transit days can significantly vary among geographies and individual distributors. We also apply judgment when estimating the total value of price concessions earned by our distributors but not claimed by the end of the reporting period. This is because there is a time lag between the price concessions earned and claimed by the distributors for any underlying resale of products. Any error in our judgment could lead to inaccurate reporting of our revenues, deferred income and allowances on sales to distributors, and net income.

Valuation of Inventories

Inventories are recorded at the lower of cost determined on a first-in-first-out basis (approximated by standard cost) or market. We establish provisions for inventory if it is in excess of projected customer demand, and the creation of such provisions results in a write-down of inventory to net realizable value and a charge to cost of goods sold. Historically, it has been difficult to forecast customer demand especially at the part-number level. Many of the orders we receive from our customers and distributors request delivery of product on relatively short notice and with lead times less than our manufacturing cycle time. In order to provide competitive delivery times to our customers, we build and stock a certain amount of inventory in anticipation of customer demand that may not materialize. Moreover, as is common in the semiconductor industry, we allow customers to cancel orders with minimal advance notice. Thus, even product built to satisfy specific customer orders may not ultimately be required to fulfill customer demand.

We routinely compare our inventory against projected demand and record provisions for excess and obsolete inventories as necessary. However, actual demand may materially differ from our projected demand, and this difference could have a material impact on our gross margin and inventory balances based on additional provisions for excess or obsolete inventory or a benefit from inventory previously written down.

Income Taxes

We make certain estimates and judgments in the calculation of tax liabilities and the determination of net deferred tax assets, which arise from temporary differences between tax and financial statement recognition methods. We record valuation allowances, when necessary, to reduce our deferred tax assets to the amount that management estimates is more likely than not to be realized. If in the future we determine that we are not likely to realize all or part of our net

deferred tax assets, an adjustment to the deferred tax asset valuation allowance would be recorded as a charge to earnings in the period such determination is made.

In addition, the calculation of our tax liabilities involves the inherent uncertainty associated with the application of complex tax laws. We are subject to examination by various taxing authorities. We believe we have adequately provided in our financial statements for additional taxes that we estimate under FIN 48, Accounting for Uncertainty in Income Taxes, may be required to be paid as a result of such examinations. If the payment ultimately proves to be unnecessary, the reversal of the tax liabilities would result in tax benefits being recognized in the period we determine the liabilities are no longer necessary. If an ultimate tax assessment exceeds our estimate of tax liabilities, an additional charge to expense will result. See Note 11 - Income Taxes to our consolidated financial statements for additional information.

We calculate our current and deferred tax provision based on estimates and assumptions that could differ from the actual results reflected in income tax returns filed. Adjustments for differences between our tax provisions and tax returns are recorded when identified, which is generally in the third or fourth quarter of our subsequent year.

Stock-based Compensation

We account for stock-based compensation in accordance with the provisions of Statement of Financial Accounting Standards ("SFAS") No. 123 (revised 2004), Share-Based Payment ("SFAS 123(R)"). Under the fair value recognition provisions of SFAS 123(R), stock-based payment expense is estimated at the grant date based on the fair value of the award and is recognized as expense ratably over the requisite service period of the award. Determining the appropriate fair value model and calculating the fair value of stock-based awards requires judgment, including estimating stock price volatility, forfeiture rates and expected life.

Upon adoption of SFAS No. 123(R) on December 31, 2005, we selected the Black-Scholes option pricing model as the most appropriate method for determining the estimated fair value for stock-based awards. The Black-Scholes model requires the use of highly subjective and complex assumptions which determine the fair value of stock-based awards, including the option's expected term and the price volatility of the underlying stock. Our current estimate of volatility is based on a blend of average historical and implied volatility for publicly traded options on our stock with a term of one year or more. To the extent volatility of our stock price increases in the future, our estimates of the fair value of options granted in the future could increase, thereby increasing stock-based payment expense in future periods. In addition, we apply an expected forfeiture rate when amortizing stock-based payment expense. Our estimate of the forfeiture rate is based primarily upon our historical experience. To the extent we revise this estimate in the future, our stock-based payment expense could be materially impacted in the quarter of revision, as well as in following quarters. We derive the expected term assumption based on our historical settlement experience. In the future, as empirical evidence regarding these input estimates is available to provide more directionally predictive results, we may change or refine our approach of deriving these input estimates. These changes could impact our fair value of stock options granted in the future. See Note 10 - Stock-based compensation to our consolidated financial statements for further information regarding the valuation of stock-based compensation.

Results of Operations

On September 23, 2008, our board of directors approved a change in our fiscal year end from the Friday nearest December 31 to December 31 of each year. This change is effective beginning with our fiscal year 2008 and has no impact on our consolidated financial statements for any previously reported period. As a result of the change in our fiscal year end, our fiscal year ended December 31, 2008 (2008) contains 369 days and our fiscal years ended December 28, 2007
(2007) and December 29, 2006 (2006) each contain 364 days.

Results of operations expressed as a percentage of net sales were as follows:

                                                               2008    2007 (1)    2006 (1)
Net sales                                                      100%        100%        100%

Cost of sales                                                   33%         35%         33%
Gross margin                                                    67%         65%         67%

Research and development expense                                19%         21%         19%

Selling, general, and administrative expense                    19%         22%         24%

Compensation expense (benefit) - deferred compensation plan     -1%          1%           -

Loss (gain) on deferred compensation plan securities             1%         -1%           -

Interest income and other                                       -2%         -5%         -4%
. . .